1 10.3125 gb/s retiming dual-channel transceiver isl37231 the isl37231 is an advanced dual-channel, dual-simplex retimer for active copper cable applications. endowed with sophisticated functions, such as media optimized (pcb or cable) and adaptive equalizatio n, de-emphasis, and signal retiming, this ic fortifies sensitive links that break with lesser retiming solutions. the device contains high performance mixed signal processing techno logy to provide a maximally robust signal integrity solution for datacenter and consumer applications. such processing includes up to 25db of media-optimized equalization and versatile retiming capabilities to reset link jitter budgets. the isl37231 provides this high level of performance while significantly reducing power co nsumption relative to other active cable solutions. at well below 500mw, the operating power is the lowest in class, and a sleep mode function can be invoked to reduce the power to a miniscule 3mw. to facilitate ease of system integration, the isl37231 provides advanced diagnostic capabilities in the form of loopback and high-resolution on-chip eye monitor functions, both accessed via a uart interface. the isl37231 is optimized to wo rk in conjunction with the isl80083 power management ic, however, it will also operate with appropriate discrete compon ents (voltage regulators and a 33mhz crystal oscillator). features ? industry?s lowest power and highest performance 10.3125gbps active cable solution for stp and twin-axial cables ? supports 64b/66b encoding ? fully retimed low jitter outputs ? up to 16.5db of adjustable (or adaptive) receiver-side equalization ? 9db output de-emphasis ? supports independent ssc on each channel ? on-chip microcontroller and eye monitor ? multiple loopback modes ? low power (<420mw) operation with 3mw sleep mode ? ultra-small 5mmx5mm aqfn package applications ?thunderbolt ? active cables ? proprietary high-speed active cable assemblies benefits ?thinner gauge cable ? extends cable reach ?improved ber pwr gnd tx1 rx1 tx2 rx2 eq cdr eq cdr eq cdr eq cdr isl37231 isl80083 eeprom pwr clk reset sda scl c ai2 ai1 bo1 bo2 ao2 ao1 bi1 bi2 cable connector pwr gnd rx1 tx1 rx2 tx2 isl37231 isl80083 eeprom pwr clk reset sda scl c bo2 bo1 ai1 ai2 bi2 bi1 ao1 ao2 cable connector eq cdr eq cdr eq cdr eq cdr cable media active cable figure 1. typical application de de de de de de de de caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. january 25, 2013 fn8266.1
isl37231 2 fn8266.1 january 25, 2013 pin configuration isl37231 (69 ld aqfn) top view ordering information part number (notes 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL37231DRAZ-TS (note 1) isl372 31draz 0 to +85 69 ld high density array (aqfn) package (7? 100 pcs.) c69.5x5b isl37231draz-t7 (note 1) isl372 31draz 0 to +85 69 ld high density array (aqfn) package (7? 1k pcs.) c69.5x5b isl37231draz isl372 31draz 0 to +85 69 ld high density array (aqfn) package c69.5x5b notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs co mpliant and compatible with both snpb an d pb-free soldering operations. intersil pb-f ree products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020 3. for moisture sensitivity level (msl), please see device information page for isl37231 . for more information on msl please see techbrief tb363 . exposed pad a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a32 a31 a30 a29 a28 a27 a26 a25 a24 a23 a22 a42 a41 a40 a39 a38 a37 a36 a35 a34 a33 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 r1 r2 r4 r3
isl37231 3 fn8266.1 january 25, 2013 pin functions and definitions pin name pin number direction description ain1[p,n] a1, a42 input high-speed differential input for on-ramp (device to cable) channel 1, cml. the use of series 220nf, low esl/esr, mlcc capacitors with at least 8ghz frequency response is recommended. gnd a2, a10, a13, a16, a17, a20, a23, a30, a31, a34, a37, a38, a41, b4, b6, b7, b16, b19, b20, b26, b27, exposed pad ground. for proper electrical and thermal perfor mance, each of these pads must be connected to the pcb ground plane. for the exposed pa d, 3x5 or 4x5 via pattern is recommended, assuming 0.004" diameter vias. xtal[p,n] a3, b1 input external 33mhz crystal oscillator input/output. an external 33mhz clock source (1v cmos logic level) can optionally be connected xtalp, in which case xtaln must be left floating. a differential 33mhz clock source (1v cmos logi c levels) can be input on xtalp and xtaln if oscmode (pin a29) is pulled high to 1.8v. autx1 a4 output auxiliary uart output 1. autx1 can be configur ed via the on-chip microcontroller as either a uart output or a gpio pin, with either 1.8v push -pull or 3.3v tolerant open drain voltage levels. aurx1 a5 input auxiliary uart data input 1, 1.8v powered cmos logic tolerant to 3.3v. eewe a6 output eeprom write enable open drain output. externally pulled high to 3.3v via a 5k ? resistor. pulled low when the isl37231 writes to an external eeprom device via the i 2 c serial interface. cfig2 a7 output thunderbolt config2 indicator output. 1.8v powered cmos logic. pulled high after the isl37231 is powered up and stable to indicate to a thunderbolt controller that a thunderbolt cable has been plugged in. oscen a8 oscillator enable. cmos logic, 1.8v. used as a deep-sleep state indicator. during normal operation, oscen is pulled high. when entering deep-sleep mode, oscen is pulled low. output is not pulled high again until transition s are detected on the urx input pin (a27). autx2 a9 output auxiliary uart output 2. autx2 can be configur ed via the on-chip microcontroller as either a uart output or a gpio pin, with either 1.8v push -pull or 3.3v tolerant open drain voltage levels. bin1[p,n] a11, a12 input high-speed differential input for off-ramp (cable to device) channel 1, cml. the use of series 220nf, low esl/esr, mlcc capacitors with at le ast 8ghz frequency response is recommended. (note 4) bout1[n,p] a14, a15 output high-speed differential output for off-ramp (cable to device) channel 1, cml. the use of series 220nf, low esl/esr, mlcc capacitors with at least 8ghz frequency response is recommended. bout2[p,n] a18, a19 output high-speed differential output for off-ramp (cable to device) channel 2, cml. the use of series 220nf, low esl/esr, mlcc capacitors with at least 8ghz frequency response is recommended. bin2[n,p] a21, a22 input high-speed differential input for off-ramp (cable to device) channel 2, cml. the use of series 220nf, low esl/esr, mlcc capacitors with at le ast 8ghz frequency response is recommended. (note 4) lsen a24 output level shift enable output. 1.8v powered cmos logi c. pulled high to indicate an operational uart interface to the isl37231. when pulled low, utx (pin a28) is set to a high impedance state. scl a25 serial interface clock. open drain output, externally pulled high to 3.3v via a 5k ? resistor. i 2 c clock, recommended clock speed is 400khz. sda a26 serial interface data. open drain output, externally pulled high to 3.3v via a 5k ? resistor. bi-directional data from/to i 2 c bus. urx a27 input uart data input. 1.8v powered cmos logic, but urx is 3.3v tolerant. when the isl37231 is in ?sleep? mode, a h to l transition on urx causes the isl37231 to drive oscen high. utx a28 output uart data tri-statable output. 1.8v powered cmos logic. utx is set to a high impedance state when the uart interface is not in use and lsen is pulled low. if utx interfaces to a 3.3v powered uart, then a level translator ic may be needed. oscmode a29 input oscillator mode. cmos logic, 1.8v, internally pulled low. when oscmode is low, the xtalp and xtaln input pins (a3 and b1) are configured for op eration with an external crystal or with an external single-ended clock on xtalp (xtaln must be left floating in this latter case). when oscmode is pulled high, the xtalp and xtaln inpu t pins are configured for operation with an external differential clock.
isl37231 4 fn8266.1 january 25, 2013 ain2[p,n] a32, a33 input high-speed differential input for on-ramp (pcb to cable) channel 2, cml. the use of series 220nf, low esl/esr, mlcc capacitors with at least 8ghz frequency response is recommended. aout2[n,p] a35, a36 output high-speed differential output for on-ramp (pcb to cable) channel 2, cml. (note 4) aout1[p,n] a39, a40 output high-speed differential output for on-ramp (pcb to cable) channel 1, cml. (note 4) avdd1 b2, r1, r2, r3, r4 (note 5) 1.0v analog supply voltage. the use of parallel 100pf and 10nf decoupling capacitors to ground is recommended for each of these pins/rails for broad high-frequency noise suppression. avdd18 b3 1.8v analog supply voltage. the use of parallel 100pf and 10nf decoupling capacitors to ground is recommended for this pin for br oad high-frequency noise suppression. nc b4, b6, b7, b13, b14, b19, b20, b26, b27 no connection. do not connect to these pins. dvdd b5, b15 1.0v digital supply voltage. the use of parallel 100pf and 10nf decoupling capacitors to ground is recommended for these pins for broad high-frequency noise suppression. vddpllb1 b8 1.8v analog supply voltage for off-ramp channel 1. refretb1 b9 vddpll reference return path for off-ramp channel 1. rext2 b10 external reference resistor connection. recommended value of 1.18k ? . refretb2 b11 vddpll reference return path for off-ramp channel 2. vddpllb2 b12 1.8v analog supply voltage for off-ramp channel 2. aurx2 b16 input auxiliary uart input 2. cmos logic, 1.8v (tolerant to 3.3v). vddpst b17 1.8v digital supply voltage. the use of parallel 100pf and 10nf decoupling capacitors to ground is recommended for each of these pins for broad high-frequency noise suppression. reset b18 input cmos logic input. 1.8v powered. resets all internal registers and memory when pulled low. vddplla2 b21 1.8v analog supply voltage for on-ramp channel 2. refreta2 b22 vddpll reference return path for on-ramp channel 2. rext1 b23 external reference resistor connection. recommended value of 1.18k ? . refreta1 b24 vddpll reference return path for on-ramp channel 1. vddplla1 b25 1.8v analog supply voltage for on-ramp channel 1. notes: 4. series coupling capacitors are required at one end of the cabl e. for best results, place the capacitors at the receiver end of the cable. the use of 220nf low esl/esr mlcc capacitors with at leas t 8ghz frequency response is recommended. 5. each power bar is independent, so they must all connect to the same 1v supply for proper circuit operation. pin functions and definitions (continued) pin name pin number direction description
isl37231 5 fn8266.1 january 25, 2013 absolute maximum rating s thermal information supply voltage (v dd to gnd, 1.0v rails) . . . . . . . . . . . . . . . . . . . . . . . . 1.1v supply voltage (v dd to gnd, 1.8v rails) . . . . . . . . . . . . . . . . . . . . . . . 1.98v 1v pin input voltage (ain, bin, xtalp) . . . . . . . . . . . . . . . . . . . . . . . . . 1.1v 1.8v pin input voltage (all non 3.3v tolerant logic inputs) . . . . v dd + 0.2v 3.3v tolerant i/o pin voltage (eew e, sclk, sda, urx, autx, aurx, reset ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6v esd ratings human body model (all pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25kv charged device model (all pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kv machine model (all pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200v latch-up (per jedec jesd78, level 2, class a) . . . . . . . . . . . . . . . . +85c thermal resistance (typical) ja (c/w) jc (c/w) 69 ld aqfn package (notes 6, 7) . . . . . . . 31.8 2.5 operating ambient temperature range . . . . . . . . . . . . . . . . 0c to +85c storage ambient temperature range. . . . . . . . . . . . . . . -55c to +150c maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 6. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 . 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. operating conditions boldface limits apply across the operating temperature range, 0c to +85c. parameter symbol condition min (note 12) typ max (note 12) units 1.0v supply voltage avdd1, dvdd 0.95 1.0 1.05 v 1.8v supply voltage avdd18, vddpll, vddpst 1.71 1.8 1.89 v operating ambient temperature t a 0 25 85 c baud rate nrz data applied to any channel 9.95 10.3125 10.4 gbps logic i/o specifications boldface limits apply across the operat ing temperature range, 0c to +85c. parameter symbol condition min (note 12) typ max (note 12) units input leakage current i leak pins urx, aurx1, aurx2, reset -1 0.1 1 a pull-down resistor current i pulldown oscmode. v in = v dd18 103 a input high voltage v ih pins urx, aurx1, aurx2, reset , oscmode 23.4 v input low voltage v il pins urx, aurx1, aurx2, reset , oscmode 00.7 v output low voltage v ol i ol = 2ma 00.4 v output high voltage v oh i oh = 2ma 1.4 v dd18 v
isl37231 6 fn8266.1 january 25, 2013 electrical characteristics t a = +25c, v dd1 = 1.0v, v dd18 = 1.8v, unless otherwise noted parameters symbol condition min (note 12) typ max (note 12) units notes 1.0v supply current (combination of all 1v supplies) i dd1 both lanes active, after equalizer has trained and is static, no eye monitors enabled 430 510 ma no lanes active, but microcontroller awake 85 150 ma sleep mode 4 ma 8 1.8v supply current (combination of all 1.8v supplies) i dd18 both lanes active, after equalizer has trained and is static, no eye monitors enabled 25 55 ma no lanes active, but microcontroller awake 9 20 ma sleep mode 330 a 8 return loss limit (differential) s dd 11 s dd 22 0.05ghz to 2ghz -10 db 9 2ghz to 5.2ghz -6 db 9 5.2ghz to 7ghz -5 db 9 return loss limit (common mode) s cc 11 s cc 22 10mhz to 5ghz -5 db 9 return loss limit (diff. to com. conversion) s cd 11 s cd 22 10mhz to 5ghz -20 db 9 input equalization range eq gain at 5ghz compared to dc. set to minimum gain 6 db 10 eq gain at 5ghz compared to dc. set to maximum gain 16.5 db 10 input equalization increment 10 steps covering the equalization range 1.5 db output de-emphasis level range off-ramp channels optimized for pcb dielectric loss. on-ramp channels optimized for cable skin loss. minimum setting 0 db off-ramp channels optimized for pcb dielectric loss. on-ramp channels optimized for cable skin loss. maximum setting 9 db de-emphasis increment 1db number of de-emphasis taps 3 11 output differential amplitude range v out minimum drive setting 200 mv p-p maximum drive setting 950 mv p-p output differential amplitude increment 15 uniform steps 50 mv p-p output transition time t r , t f 20% to 80% 45 ps jitter transfer function bandwidth 5 mhz total output jitter 1e-13 ber; prbs-31; no low frequency input periodic jitter 0.3 ui p-p ssc down spreading amplitude tolerance 0.5 % ssc modulation rate tolerance 33-37 khz notes: 8. the specified sleep mode currents can only be achieved when th e isl37231 is used in conjunct ion with the isl80083 power manag ement ic. 9. measured with a vector network analyzer with 100 ? -diff impedance and the isl37231 input/output impedance at setting 0x07 (i.e. 100 ? -diff). 10. the equalization response includes all effects starting from the ic input pins up to the output of the equalization stage. 11. three de-emphasis taps composed of: 1 pre-cursor + main + 1 post-cursor. 12. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
isl37231 7 fn8266.1 january 25, 2013 operation the isl37231 is a robust signal conditioner that ensures maximum performance across a variety of time-varying and unpredictable environments. endowed with functions, such as transmit and receive equaliza tion, signal retiming, and programmable impedance termination, this ic fortifies sensitive links that break with other retiming -based solutions. to facilitate systems analysis, the isl37231 addi tionally provides visibility of link conditions by way of loopback modes, prbs generators with error counters, and an on-chip eye-monitor. equalization the isl37231 equalizes each received signal with a highly adjustable equalizer. each received signal is equalized with a five stage continuous-time linear filter that can be optimized for either copper cable skin loss or diel ectric loss. the amount of equalization is selectable between 0db and 16.5db of compensation in increments of 1.5db. because the filter is phase/jitter-optimized, the maximum 16.5db compensation level yields very low jitter for its targeted 2m (~20db) 34awg cable length. in addition to supporting a wide variety of programmable settings, all channel equalizers can be trained upon power up to minimize jitter. the training of all channels is completed within 2.5ms of receiving valid data on the input ports after power up. retiming to provide maximum system robu stness, the isl37231 retimes each of the four data paths in the device prior to output. with independent plls for each channel, the device can operate each channel with asynchronous baud rates thereby permitting a high degree of system flexibility. examples where such flexibility is crucial include independent or staggered ssc rates across different channels and asymmetr ic transmission where up and down-stream channels operate at different baud rates. each retimer has high input jitt er tolerance and can output less than 0.3ui of total jitter (provi ded the inherent rj of the test equipment is de-embedded and no input low-frequency periodic jitter is present). output de-emphasis the drive level output of any channel is adjustable from 200 to 950mvppd rail-to-rail (170 to 807.5mvppd eye height) in 16 equal increments. each driver supports output equalization with one tap of pre-cursor and one tap of post-cursor de-emphasis. the gains on the pre and post-cursor taps are adjustable between 0 and -1 relative to the main tap in increments of 1/128. the output amplitude and de-emphasis for each channel can be independently programmed to accommodate routing variation between lanes. loopback to facilitate system diagnostics, a loopback mode is available for each signal direction. in particular, for each lane, two loopback paths are provided: ? near-end/pcb loopback: the received on-ramp signal is directed back into the off-ramp output driver. this includes pcb equalization, limiting, retiming, and pcb de-emphasis. ? far-end/cable loopback: the re ceived off-ramp signal is directed back into the on-ramp output driver. this includes cable equalization, limiting, re timing, and cable de-emphasis. eye monitor for accurate and detailed analys is of signal integrity, each channel in the isl37231 can provide an on-chip eye-diagram of its respective equalizing filter output. this eye diagram can be used to evaluate jitter and eye height at the input of the retime circuit?s slicer. the eye monitor (in conjunction wi th the on-chip microcontroller) generates up to a 50 pixel x 50 pixel resolution eye-diagram (i.e. down to 0.02 ui resolution in the time domain and 12mv resolution in the voltage domain) that can be read over the uart interface. the output eye diagram represents an estimated probability density function for the equalized signal under investigation. besides providing a full eye-diagra m, the eye-monitor can also be directed to output only the temp oral and/or voltage eye-opening for a more concise signal fidelity assessment (i.e., jitter and eye height, respectively). polarity inversion to accommodate uncertainty in signal polarity (as may be associated with differential cable receive pairs), each channel can be independently programmed to invert its polarity. on-chip microcontroller an internal microcontroller is us ed to manage the operation of the isl37231. the microcontroller communicates with the system host over a uart interface. because the isl37231 uart interface operates at 1.8v, an interfacing ic (such as the isl80083) is required for applications needing 3.3v levels and tri-state (push/pull/no-load) operation. the microcontroller also includes an i 2 c interface where the isl37231 serves as the master. this i 2 c bus is used to: ? instruct a power-regulator providing the 1.0v supply that the system is entering sleep mode and power can be removed from non-critical 1.0v rails for maximum power savings during sleep state. ? load firmware from an external eeprom.
isl37231 8 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8266.1 january 25, 2013 for additional products, see www.intersil.com/product_tree about q:active? technology intersil has long realized that to enable the complex server clusters of next generation data centers, it is critical to manage the signal integrity issues of elec trical interconnects. to address this, intersil has developed its groundbreaking q:active? product line. by integrating its analog ics inside cabling interconnects, intersil is able to achieve unsurpassed improvements in reach, power co nsumption, latency, and cable gauge size as well as increased airflow in tomorrow?s data centers. this new technology transforms passive cabling into intelligent ?roadways? that yiel d lower operating expenses and capital expenditures for the expanding datacenter. intersil lane extenders allow greater reach over existing cabling while reducing the need for thicker cables. this significantly reduces cable weight and clutter, increases airflow, and improves power consumption. about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: isl37231 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change january 17, 2013 fn8266.1 changed typ values for ?i dd1 ? on page 6. december 19, 2012 fn8266.0 initial release
isl37231 9 fn8266.1 january 25, 2013 package outline drawing c69.5x5b 69 lead aqfn 5x5 package with 0.40 pitch rev 1, 12/12 bottom view symbol millimeter inch min nom. max min nom. max a - - 0.85 - - 0.033 a3 0.020 0.050 0.080 0.001 0.002 0.003 a2 0.640 0.675 0.710 0.025 0.027 0.028 a1 0.120 0.130 0.140 0.005 0.005 0.006 b 0.170 0.200 0.230 0.007 0.008 0.009 d 4.900 5.000 5.100 0.193 0.197 0.201 d2 2.780 2.880 2.980 0.109 0.113 0.117 e 4.900 5.000 5.100 0.193 0.197 0.201 e2 1.940 2.040 2.140 0.076 0.080 0.084 et 0.400 0.016 er 0.400 0.016 k 0.200 0.250 0.300 0.008 0.010 0.012 k1 0.160 0.210 0.260 0.006 0.008 0.010 l1 0.160 0.210 0.260 0.006 0.008 0.010 l2 0.230 0.280 0.330 0.009 0.011 0.013 s1 0.260 0.310 0.360 0.010 0.012 0.014 s2 0.330 0.380 0.430 0.013 0.015 0.017 w 0.150 0.180 0.210 0.006 0.007 0.008 tolerances of form and position aaa 0.100 0.004 bbb 0.100 0.004 ddd 0.050 0.002 ccc 0.100 0.004 eee 0.100 0.004 fff 0.100 0.004 note: 1. controlling dimension: mm section c-c top view detail "b" (3:1)(69x) a b pin 1 e c c c.l(pkg.) c.l(pkg.) d2 e2 k1 c a a1 a2 a3 er er et d et 0.00 k 0.00 2.50 pkg. 2.50 pkg. 2.50 pkg. 2.50 pk g. b2 b1 b3 b4 b16 b17 b15 b14 a27 a28 a29 a30 a26 a25 a24 b9 b10 b11 b12 b13 b8 b7 b6 a17 a18 a19 a20 a21 a16 a15 a14 a13 a12 a23 a22 a6 a5 a4 a3 a7 a8 a9 a10 a11 b22 b21 b20 b19 b18 b23 b24 b25 b26 a37 a36 a35 a34 a33 a38 a39 a40 a41 a42 a2 a1 a31 a32 b5 b27 (pin 1 corner) "b" l1 l2 2.19 1.80 1.83 1.60 1.40 1.44 0.125 0.125 1.65 1.83 1.80 2.19 1.60 1.40 1.44 1.02 1.20 1.23 1.41 1.60 1.72 2.00 2.12 0.92 1.00 1.02 1.20 1.23 1.41 1.60 1.72 2.00 2.12 0.95 0.95 1.56 1.34 1.65 pwr1 pwr2 pwr3 pwr4 w aaa c aaa c corner ccc c eee c fff c a b m fff c a b m b bbb c a b ddd c s2 s1
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